The degradation of device threshold voltage under the presence of constant electrical and thermal stress is becoming a significant reliability issue in current complementary metal oxide semiconductor (CMOS) technologies. Bias temperature stress under constant voltage results in the generation of interface traps between the gate oxide and silicon substrate, which causes the threshold voltage of the device to increase, resulting in a reduced drive current for the device. Until recently, the NBTI (Negative Bias Temperature Instability) effect was considered to be more severe for p-type field effect transistors (PFETs) than the corresponding PBTI (Positive Bias Temperature Instability) effect on n-type field effect transistors (NFETs). However, with the use of metal gates and high-k gate dielectrics, PBTI is becoming an equivalently important concern. These phenomena were identified by S. Zafar, et al. in “A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates,” Symposium of VLSI Technology, June 2006.
Presently, NBTI test-circuits employ a simple ring oscillator circuit 100, as shown in FIG. 1. The frequency of ring oscillator 100 is measured before stress. In stress mode, the ring is disabled from oscillation and the supply voltage and/or temperature are increased to facilitate an accelerated stressing of the devices. Since PBTI has been considered insignificant, the impact of stress on the NFETs 102 has been ignored. After suitably stressing the ring-oscillator circuit 100, its frequency is measured again, and the difference in the pre- and post-stress frequencies is a direct indication of the extent of NBTI related degradation of the PFET devices 104 in the circuit. Note that circles 106 indicate PMOS devices under stress while circle 108 indicates and NMOS device under stress. Note also that the connection between output 110 and input 112 is omitted for clarity, and that transistors are referred to herein generically as devices.
U.S. Pat. No. 6,476,632 to La Rosa, et al. discloses a ring oscillator design for metal oxide semiconductor field effect transistor (MOSFET) device reliability investigations and its use for in-line monitoring. A method of determining the effect of the degradation of MOSFETs on the frequency of a Ring Oscillator (RO) consisting of an odd prime number of inverter stages, each of the inverters stages having an NMOS and a PMOS field-effect transistor, is described. The method includes the steps of: a) selecting one inverter from the inverter stages of the RO, the selected inverter having testable nodes, the testable nodes being connected to inputs and outputs of the NMOS and a PMOS field-effect transistor (FET) forming the selected inverter; b) simultaneously stressing under a set of stress conditions 1) all of the NMOS FETs of each of the inverter stages, 2) all of the PMOS FETs, and 3) all of the NMOS FETs and PMOS FETs in the RO; c) measuring a shift in selected device parameters in the selected inverter; d) measuring a frequency degradation of the entire RO; and e) establishing a relationship between the shift in the device parameters and the frequency degradation and relating the relationship to a known degradation mechanism. Furthermore, on-chip pass gates controlled by appropriate off-chip DC voltage signals, allow parallel DC stressing, as well as forcing an off-chip AC voltage waveform to a given MOSFET type device (either PMOSFET or NMOSFET) on every inverter stage of the RO. The RO circuit makes it possible to investigate the effect on the RO frequency degradation, caused by any DC MOSFET degradation mechanism as well as by any external AC voltage waveform known to be representative of a critical circuit operation. Thus, the dependence of the RO frequency on device degradation mechanisms activated during a critical circuit operation can be carefully investigated and quantified.